1. Field of the Invention
The present invention relates to multiprecision floating-point processors in general and in particular to a method and apparatus for identifying the precision of input and output operands in a multiprecision floating-point processor using an identifying precision tag with each operand.
2. Description of Prior Art
A number of floating-point formats are currently used in floating-point processors, such as for example, IEEE, DEC D, DEC G AND IBM.
In each of the above-identified formats, an operand can be represented with a selected degree of precision, e.g. single or double precision. For example, in the IEEE floating-point format, a single precision operand comprises 32 bits among which, one bit comprises a sign bit, 8 bits comprise an exponent and 23 bits comprise a fraction. The same operand represented with double precision comprises 64 bits among which, one bit comprises a sign bit, 11 bits comprise an exponent and 52 bits comprise a fraction.
Regardless of the format used, the precision of each of the input and output operands in a particular arithmetic operation usually depends on the nature of the operation and the resolution and accuracy desired. For example, in forming a sum of a plurality of products having the form a.sub.1 b.sub.1 +a.sub.2 b.sub.2 . . . a.sub.n b.sub.n, both single precision and double precision operands are usually involved. In such operations, the input operands which correspond to the individual multiplicands and multipliers are often provided as single precision operands, while the output operand corresponding to the product of the multiplication is often provided for purposes of accuracy and resolution as a double precision operand. Therefore, when obtaining the sum of a plurality of products, the ALU used must be selectively controllable to operate on two single precision input operands to produce a double precision output operand when forming the products and thereafter controllable to operate on two double precision operands when forming the sum of the products.
In other arithmetic operations it may be necessary for the ALU to operate on mixed precision operands simultaneously. For example, in certain cases, one of two input operands may be a single precision operand and the other a double precision operand with the output operand being either a single or a double precision operand. In such cases, the ALU must be responsive to a control signal corresponding to the precision of the individual operands.
Since the requirements of various arithmetic operations may comprise both single and double precision input and output operands as well as mixed precision operands, the ALU used should be capable of handling mixed precision operands in general. Fortunately, ALU's which are capable of handling mixed precision operands are known. For example, the Intel 8087 is such an ALU.
In operation, an instruction word for the Intel 8087 specifies the precisions of the input operands and the output operand in addition to the operation to be executed.
While mixed precision arithmetic operations are possible using prior known methods and apparatus as described above, a serious disadvantage of the prior known methods and apparatus is that, heretofore, it has been necessary to keep track of the precision of each operand and to generate instruction words containing the necessary precision information in a timely manner off-chip using software specially designed therefor. These requirements have typically placed a heavy burden on the software programmer and have necessitated additional off-chip storage to facilitate keeping track of the precision of each operand and the generation of the necessary instruction words.